`timescale 1ns / 1ps
/*
 Copyright 2020 Sean Xiao, jxzsxsp@qq.com
 
 Licensed under the Apache License, Version 2.0 (the "License");
 you may not use this file except in compliance with the License.
 You may obtain a copy of the License at
 
 http://www.apache.org/licenses/LICENSE-2.0
 
 Unless required by applicable law or agreed to in writing, software
 distributed under the License is distributed on an "AS IS" BASIS,
 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 See the License for the specific language governing permissions and
 limitations under the License.
 */

//`include "fii_rv32_def.v"
module regfile_I(
    input  sys_clk,
    
    input  i_EXE_vld,
    
    input  [ 4: 0 ] i_rs1_idx,
    input  [ 4: 0 ] i_rs2_idx,
    
    output [ 31: 0 ] o_rs1_val,
    output [ 31: 0 ] o_rs2_val,

    output o_wb_rdy,
    input  i_wb_wen,
    input  [ 4: 0 ] i_wb_rd_idx,
    input  [ 31: 0 ] i_wb_val
);

wire [ 31: 0 ] rf_r [ 31: 1 ];
wire [ 31: 1 ] rf_wen;


genvar i;
generate
    for ( i = 1; i < 32; i = i + 1 )
    begin : REG
        assign rf_wen[ i ] = i_EXE_vld & i_wb_wen & ( i_wb_rd_idx == i ) ;
        yue_dffl #( 32 ) rf_dffl ( rf_wen[ i ], i_wb_val, rf_r[ i ], sys_clk );
    end
endgenerate


`ifdef sim
    assign o_rs1_val = ( i_rs1_idx == 0 ) ? 32'b0 :
        ( rf_r[ i_rs1_idx ] == 32'hxxxxxxxx ) ? 32'b0 : rf_r[ i_rs1_idx ];
    assign o_rs2_val = ( i_rs2_idx == 0 ) ? 32'b0 :
       ( rf_r[ i_rs2_idx ] == 32'hxxxxxxxx ) ? 32'b0 : rf_r[ i_rs2_idx ];
`else
    assign o_rs1_val = ( i_rs1_idx == 0 ) ? 32'b0 : rf_r[ i_rs1_idx ];
    assign o_rs2_val = ( i_rs2_idx == 0 ) ? 32'b0 : rf_r[ i_rs2_idx ];
`endif

assign o_wb_rdy = 1'b1;


endmodule
